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74HCT109PW,112

Flip-Flop, Complementary Output, Positive Edge, 74HCT109, JK, 20 ns, 61 MHz, 4 mA, TSSOP

NEXPERIA 74HCT109PW,112
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Manufacturer:
NEXPERIA NEXPERIA
Manufacturer Part No:
74HCT109PW,112
Order Code:
1631677
Technical Datasheet:
74HCT109PW,112   Datasheet
See all Technical Docs

Product Overview

The 74HCT109PW is a positive-edge trigger Dual J K\ Flip-flop with set and reset. This high-speed Si-gate CMOS device is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The dual positive-edge triggered J K\ flip-flops with individual J, K\ inputs, clock (CP) inputs, set (SD\) and reset (RD\) inputs, also complementary Q and Q\ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K\ inputs control the state changes of the flip-flops as described in the mode select function table. The J and K\ inputs must be stable one set-up time prior to the low-to-high clock transition for predictable operation. The J K\ design allows operation as a D-type flip-flop by tying the J and K\ inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
  • J, K\ Inputs for easy D-type flip-flop
  • Toggle flip-flop
  • Standard output capability
  • ICC Category

Applications

Industrial, Consumer Electronics, Computers & Computer Peripherals

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.

Product Information

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74HCT109

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JK

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20ns

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61MHz

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4mA

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TSSOP

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16Pins

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Positive Edge

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Complementary

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4.5V

:
5.5V

:
74HCT

:
74109

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-40°C

:
125°C

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-

:
-

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MSL 1 - Unlimited
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Technical Docs (3)

CAD Downloads

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Terms and Conditions

CAD Models - Notice
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Use of these CAD models and other options provided are downloaded and used entirely at your own risk and by continuing you confirm acceptance of the above.

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