AS4C16M16MD1-6BCN

AS4C16M16MD1-6BCN is a 256Mb mobile 268,435,456bits synchronous double data rate dynamic RAM. Each 67,108,864 bits bank is organized as 8,192 rows by 512 columns by 16bits, fabricated with Alliance Memory's high-performance CMOS technology. This device uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls. The range of operating frequencies, programmable burst lengths, and programmable latencies allow the same device to be useful for a variety of high bandwidth and high-performance memory system applications.

• VDD/VDDQ = 1.7 to 1.95V, data width: x16, bidirectional, data strobe (DQS)
• Partial array self-refresh (PASR), auto temperature-compensated self-refresh (ATCSR)
• Power down mode, deep power down mode (DPD mode), programmable output buffer driver strength
• Four internal banks for concurrent operation, data mask (DM) for write data
• Clock stop capability during idle periods, auto pre-charge option for each burst access
• Double data rate for data output, differential clock inputs (CK and active-low CK )
• Burst length: 2, 4, 8 and 16, burst type: sequential or interleave
• 64ms refresh period, LVCMOS interface, 166MHz clock rate
• 60-ball FPBGA package
• Extended temperature range from -30°C to +85°C