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Quantity | Price |
---|---|
1+ | HK$59.310 |
10+ | HK$55.290 |
25+ | HK$53.610 |
50+ | HK$52.300 |
100+ | HK$50.150 |
250+ | HK$48.650 |
500+ | HK$47.710 |
Product Information
Product Overview
MT41K256M16TW-107 AIT:P is a DDR3L SDRAM. This DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.
- Differential clock inputs (CK, CK#), 8 internal banks
- Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
- Programmable CAS (READ) latency (CL), programmable posted CAS additive latency (AL)
- Programmable CAS (WRITE) latency (CWL)
- Self-refresh temperature (SRT), automatic self refresh (ASR)
- Write levelling, multipurpose register, output driver calibration
- 256 Meg x 16 configuration
- 1866MT/s data rate, 13.91ns CL, AEC-Q100 qualified, PPAP submission
- 96-ball FBGA package
- Industrial temperature range from -40°C ≤ TC ≤+95°C
Warnings
Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.
Technical Specifications
DDR3L
256M x 16bit
FBGA
1.35V
-40°C
-
4Gbit
933MHz
96Pins
Surface Mount
95°C
No SVHC (17-Dec-2015)
Technical Docs (2)
Legislation and Environmental
Country in which last significant manufacturing process was carried outCountry of Origin:Singapore
Country in which last significant manufacturing process was carried out
RoHS
RoHS
Product Compliance Certificate