MT41K256M8DA-125:K

MT41K256M8DA-125:K is a DDR3L SDRAM that uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clock cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. It operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.

• 256 Meg x 8 configuration, tCK = 1.25ns, CL = 11 speed grade
• VDD = VDDQ = 1.35V (1.283 to 1.45V)
• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe, 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#), 8 internal banks
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL), programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• 78-ball FBGA package
• Commercial temperature range from 0 to 95°C

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.