74LVC1G57GW,125

74LVC1G57GW,125 is a configurable multiple function gate with schmitt-trigger inputs. This device can be configured as any of the following logic functions AND, OR, NAND, NOR, XNOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• Wide supply voltage range from 1.65V to 5.5V, complies with JEDEC standard
• Overvoltage tolerant inputs to 5.5V, high noise immunity
• CMOS low power dissipation, latch-up performance exceeds 250mA
• Direct interface with TTL levels, IOFF circuitry provides partial power-down mode operation
• Input leakage current is ±0.1μA typ at (VI= 5.5V or GND;VCC = 0V to 5.5V, -40°C to +85°C)
• Supply current is 0.1μA typ at (VI=5.5V or GND; IO = 0A;VCC = 1.65V to 5.5V, -40°C to +85°C)
• Input capacitance is 2.5pF typical at (-40°C to +85°C)
• Propagation delay is 6ns typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP6 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.