74LVC2G14GV,125

74LVC2G14GV,125 is a dual inverter with schmitt-trigger inputs. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as translator in mixed 3.3V and 5V environments. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. It complies with JEDEC standard (JESD8-7 (1.65V to 1.95V), JESD8-5 (2.3V to 2.7V), JESD8C (2.7V to 3.6V), JESD36 (4.5V to 5.5V). It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V). It is used in applications such as wave and pulse shaper, astable multivibrator, monostable multivibrator.

• Wide supply voltage range from 1.65V to 5.5V, latch-up performance exceeds 250mA
• High noise immunity, CMOS low power dissipation
• Direct interface with TTL levels, unlimited rise and fall times
• Overvoltage tolerant inputs to 5.5V, IOFF circuitry provides partial power-down mode operation
• Input leakage current is ±0.1μA typical at (VI=5.5V or GND;VCC = 0V to 5.5V, Tamb = -40 °C to +85°C)
• Supply current is 0.1μA typ at (VI=5.5V or GND;VCC = 1.65V to 5.5V;IO = 0A, Tamb = -40°C to +85°C)
• Input capacitance is 3.5pF typical at (VCC = 3.3V; VI= GND to VCC, Tamb = -40°C to +85°C)
• Propagation delay is 5.6ns typical at (VCC = 1.65V to 1.95V, Tamb = -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSOP6 package