CY7C1041GN30-10ZSXIT

CY7C1041GN30-10ZSXIT is a high-performance CMOS fast static RAM organized as 256K words by 16bits. Data writes are performed by asserting the Chip Enable (active-low CE) and Write Enable (active-low WE) inputs LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (active-low BHE) and Byte Low Enable (active-low BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Data reads are performed by asserting the Chip Enable (active-low CE) and Output Enable (active-low OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (active-low BHE or active-low BLE) to read either the upper byte or the lower byte of data from the specified address location.

• Fast asynchronous SRAM family, 4Mbit density, 16bits data width
• 65nm process technology, 2.2V to 3.6V voltage range, 10ns speed
• 1.0V data retention, TTL-compatible inputs and outputs
• Input leakage current is +1µA maximum at (GND < VIN < VCC)
• Operating supply current is 38mA typical at (max VCC, IOUT = 0mA, CMOS levels)
• Input capacitance is 10pF typical at ( TA = 25°C, f = 1 MHz, VCC = VCC(typ))
• Data retention current is 8mA max at (VCC = 1.2V, CE > VCC – 0.2V)
• Output leakage current is +1µA maximum at (GND < VOUT < VCC, output disabled)
• VCC for data retention is 1V min at (40°C to 85°C)
• Industrial ambient temperature range from -40°C to +85°C, 44-pin TSOP package