ATF1504AS-10JU44

The ATF15xx series high-performance, high-density Complex Programmable Logic Device (CPLD) which utilizes the electrically-erasable memory technology. With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL, SSI, MSI, LSI and classic PLDs. It enhanced routing switch matrices increases usable gate count and the odds of successful pin-locked design modifications. The ATF1504AS has up to 68 bi-directional I/O pins and four dedicated input pins. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell. Each of the 64 macrocells generates a buried feedback which goes to the global bus. Each input and I/O pin also feeds into the global bus. The switch matrix in each logic block then selects 40 individual signals from the global bus.

• High-density, high-performance, electrically-erasable complex programmable
• In-system programmability (ISP) via JTAG
• Flexible logic macrocell
• Advanced EE technology
• JTAG Boundary-scan testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 supported
• PCI-compliant
• Output enable product terms
• Transparent - latch mode
• Combinatorial output with registered feedback within any macrocell
• Three global clock pins
• ITD (Input transition detection) circuits on global clocks, inputs and I/O
• Fast registered input from product term
• Programmable 'pin-keeper' option
• VCC Power-up reset option
• Pull-up option on JTAG pins TMS and TDI
• Advanced power management features