MTA8ATF1G64HZ-3G2R1

MTA8ATF1G64HZ-3G2R1 is a high-speed DDR4 SDRAM module that uses DDR4 SDRAM devices with two or four internal memory bank groups. DDR4 SDRAM module utilizing 4- and 8-bit-wide DDR4 SDRAM devices has four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM device has two internal bank groups consisting of four memory banks each, providing a total of eight banks. DDR4 SDRAM modules benefit from the DDR4 SDRAM's use of an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bit-wide, four-clock data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR4 module uses two sets of differential signals: DQS-t and DQS-c to capture data and CK-t and CK-c to capture commands, addresses, and control signals.

• 8GB module density, 1 Gig x 64 configuration, 25.6GB/s module bandwidth
• 0.62ns/3200 MT/s memory clock/data rate, 22-22-22 clock cycles (CL-tRCD-tRP)
• VDD supply voltage range from 1.14 to 1.26V, DRAM activating power supply range from 2.375 to 2.75V
• Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
• Low-power auto self refresh (LPASR), data bus inversion (DBI) for data bus
• On-die VREFDQ generation and calibration, single-rank, gold edge contacts
• On-board I²C serial presence-detect EEPROM, 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS)
• Fly-by topology, terminated control command and address bus
• 260-pin DIMM package, commercial operating temperature range from 0°C to 95°C