74LVC74APW-Q100J

74LVC74APW-Q100J is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (n active-low SD) and (n active-low RD) inputs, and complementary nQ and n active-low Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. This product has been qualified to the automotive electronics council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. It features ESD protection (HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000V, CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000V).

• 5V tolerant inputs for interlacing with 5V logic
• Wide supply voltage range from 1.65V to 3.6V
• CMOS low power consumption, direct interface with TTL levels
• Latch-up performance exceeds 250mA
• Input leakage current is ±0.1μA typ at (VCC = 3.6V;VI= 5.5 V or GND, -40°C to +85°C)
• Supply current is 0.1μA typ at (VCC = 3.6V;VI= VCC or GND;IO = 0A, -40°C to +85°C)
• Input capacitance is 4pF typ at (-40°C to +85°C)
• Propagation delay is 5ns typical at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP14 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.